# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 6.1.1 Build EDK_G.13
# Thu Dec 04 09:27:45 2003
# Target Board:	 Memec Design Virtex-II Pro P7-fg456 Development Board Rev 3
# Family:	 virtex2p
# Device:	 XC2VP7
# Package:	 FG456
# Speed Grade:	 -6
# Processor: Microblaze
# System clock frequency: 100 MHz
# Debug interface: On-Chip HW Debug Module
# Data Cache: 16384 Byte
# Instruction Cache: 16384 Byte
# On Chip Memory :  32 KB
# Total Off Chip Memory :  32 MB
# - SDRAM_8Mx32 =  32 MB
# ##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT RS232_RX = RS232_RX, DIR = I
 PORT RS232_TX = RS232_TX, DIR = O
 PORT LEDs_4Bit_GPIO_IO = LEDs_4Bit_GPIO_IO, VEC = [0:3], DIR = IO
 PORT SDRAM_8Mx32_SDRAM_RASn = SDRAM_8Mx32_SDRAM_RASn, DIR = O
 PORT SDRAM_8Mx32_SDRAM_CASn = SDRAM_8Mx32_SDRAM_CASn, DIR = O
 PORT SDRAM_8Mx32_SDRAM_CSn = SDRAM_8Mx32_SDRAM_CSn, DIR = O
 PORT SDRAM_8Mx32_SDRAM_CKE = SDRAM_8Mx32_SDRAM_CKE, DIR = O
 PORT SDRAM_8Mx32_SDRAM_WEn = SDRAM_8Mx32_SDRAM_WEn, DIR = O
 PORT SDRAM_8Mx32_SDRAM_Clk = SDRAM_8Mx32_SDRAM_Clk, DIR = O
 PORT SDRAM_8Mx32_SDRAM_Addr = SDRAM_8Mx32_SDRAM_Addr, VEC = [0:11], DIR = O
 PORT SDRAM_8Mx32_SDRAM_BankAddr = SDRAM_8Mx32_SDRAM_BankAddr, VEC = [0:1], DIR = O
 PORT SDRAM_8Mx32_SDRAM_DQ = SDRAM_8Mx32_SDRAM_DQ, VEC = [0:31], DIR = IO
 PORT SDRAM_8Mx32_SDRAM_DQM = SDRAM_8Mx32_SDRAM_DQM, VEC = [0:3], DIR = O
 PORT sys_rst = sys_rst_s, DIR = input
 PORT sys_clk = sys_clk_s, DIR = input, SIGIS = CLK
 PORT RS232_req_to_send = net_gnd, DIR = OUTPUT


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 16384
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 16384
 PARAMETER C_ICACHE_BASEADDR = 0x80000000
 PARAMETER C_ICACHE_HIGHADDR = 0x80FFFFFF
 PARAMETER C_ADDR_TAG_BITS = 9
 PARAMETER C_USE_DIV = 1
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_DCACHE_BASEADDR = 0x80000000
 PARAMETER C_DCACHE_HIGHADDR = 0x80FFFFFF
 PARAMETER C_DCACHE_ADDR_TAG = 9
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 PORT CLK = sys_clk_s
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
 PORT INTERRUPT = interrupt
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.b
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT OPB_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0xFFFF7000
 PARAMETER C_HIGHADDR = 0xFFFF70FF
 BUS_INTERFACE SOPB = mb_opb
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_MASK = 0x10000000
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_MASK = 0x10000000
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MEMSIZE = 16384
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 57600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_BASEADDR = 0xFFFF2000
 PARAMETER C_HIGHADDR = 0xFFFF20FF
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT RX = RS232_RX
 PORT TX = RS232_TX
 PORT Interrupt = uart_interrupt
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_4Bit
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0xFFFF5000
 PARAMETER C_HIGHADDR = 0xFFFF50FF
 BUS_INTERFACE SOPB = mb_opb
 PORT GPIO_IO = LEDs_4Bit_GPIO_IO
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_sdram
 PARAMETER INSTANCE = SDRAM_8Mx32
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 0
 PARAMETER C_SDRAM_TMRD = 15000
 PARAMETER C_SDRAM_TCCD = 1
 PARAMETER C_SDRAM_TRAS = 48000
 PARAMETER C_SDRAM_TRC = 70000
 PARAMETER C_SDRAM_TRFC = 75000
 PARAMETER C_SDRAM_TRCD = 19000
 PARAMETER C_SDRAM_TRRD = 16000
 PARAMETER C_SDRAM_TRP = 19000
 PARAMETER C_SDRAM_TREF = 64
 PARAMETER C_SDRAM_CAS_LAT = 2
 PARAMETER C_SDRAM_COL_AWIDTH = 9
 PARAMETER C_SDRAM_BANK_AWIDTH = 2
 PARAMETER C_SDRAM_AWIDTH = 12
 PARAMETER C_SDRAM_DWIDTH = 32
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_BASEADDR = 0x80000000
 PARAMETER C_HIGHADDR = 0x80FFFFFF
 BUS_INTERFACE SOPB = mb_opb
 PORT SDRAM_RASn = SDRAM_8Mx32_SDRAM_RASn
 PORT SDRAM_CASn = SDRAM_8Mx32_SDRAM_CASn
 PORT SDRAM_CSn = SDRAM_8Mx32_SDRAM_CSn
 PORT SDRAM_CKE = SDRAM_8Mx32_SDRAM_CKE
 PORT SDRAM_WEn = SDRAM_8Mx32_SDRAM_WEn
 PORT SDRAM_CLK_in = sys_clk_s
 PORT OPB_Clk = sys_clk_s
 PORT SDRAM_Clk = SDRAM_8Mx32_SDRAM_Clk
 PORT SDRAM_Addr = SDRAM_8Mx32_SDRAM_Addr
 PORT SDRAM_BankAddr = SDRAM_8Mx32_SDRAM_BankAddr
 PORT SDRAM_DQ = SDRAM_8Mx32_SDRAM_DQ
 PORT SDRAM_DQM = SDRAM_8Mx32_SDRAM_DQM
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0xffff3000
 PARAMETER C_HIGHADDR = 0xffff30ff
# 00000000000000000000000000000011
# PARAMETER C_KIND_OF_INTR = 11, DT = std_logic_vector
# PARAMETER C_KIND_OF_EDGE = 11, DT = std_logic_vector
# PARAMETER C_KIND_OF_LVL =  XX, DT = std_logic_vector
 BUS_INTERFACE SOPB = mb_opb
 PORT Irq = interrupt
 PORT Intr = uart_interrupt & timer_interrupt
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_timer
 PARAMETER INSTANCE = opb_timer_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0xffff1000
 PARAMETER C_HIGHADDR = 0xffff10ff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT Interrupt = timer_interrupt
END